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Synchronous PWM Controller with Dual Low Dropout Regulator Controllers
POWER MANAGEMENT Description
The SC1109 was designed for the latest high speed motherboards. It combines a synchronous voltage mode controller (switching section) with two low-dropout linear regulator controllers. The voltage mode controller provides the power supply for the system AGTL bus. The Dual linear controllers power the chip set and clock circuitry. The SC1109A switching section features lossless current sensing, while SC1109C provides programmable over current limit. SC1109 also utilizes latched driver outputs for enhanced noise immunity. SC1109A and SC1109C operate at a fixed frequency of 200kHz, and the SC1109B is available at a fixed frequency of 500kHz. The VTT output voltage is internally fixed at 1.2V The SC1109 linear sections are low dropout regulators designed to track the 3.3V power supply when it turns on or off. The voltage for the linear controllers LDO1, and LDO2 are 1.8V/1.5V.
SC1109
Features
Dual linear controllers LDOs track input voltage within 200mV (function of the MOSFETs used) until regulation Integrated drivers Power good signal (SC1109A, SC1109B) Soft start Lossless current sense Programmable over current limit (SC1109C) 200kHz (SC1109A, SC1109C), and 500kHz (SC1109B) fixed frequency.
Applications
Pentium(R) III Motherboards Triple power supplies
Typical Application Circuit
12V IN 5V STBY 5V IN C2 2x1500uF C3 0.1uF C5 0.1uF SC1109ACSTR or SC1109BCSTR 11 4 C6 0.1uF 5 14 POWER GOOD C9 0.1uF 12 13 15 16 VCC BCAP+ STBY BST DH BCAPSS/EN PWRGD VOSENSE GATE2 LDOS2 U1 DL GND GATE1 LDOS1 8 6 2 1 PHASE 3 10 9 7 R1 2.2 C4 0.1uF C1 0.1uF
+
Q1 MOSFET N L1 4uH C7 3x1500uF Q2 MOSFET N
1.2V 6A
VTT
R2 2.2
+
C8 0.1uF
3.3V IN Q3 MOSFET N LDO2 = 1.5V + Q4 MOSFET N LDO1 = 1.8V C12 330uF
+
C10 330uF +
C11 330uF
12V IN 5V STBY 5V IN C2 2x1500uF C3 0.1uF C13 1nF R3 TBD C5 0.1uF U1 11 4 C6 0.1uF 5 14 OCSET C9 0.1uF 12 13 15 16 VCC BCAP+ STBY BST DH BCAPSS/EN OCSET VOSENSE GATE2 LDOS2 DL GND GATE1 LDOS1 8 6 2 1 PHASE 3 10 9 7 R1 2.2 C4 0.1uF C1 0.1uF
+
Q1 MOSFET N L1 4uH C7 Q2 3x1500uF MOSFET N
1.2V 6A
VTT
R2 2.2
+
C8 0.1uF
SC1109CCSTR
3.3V IN Q3 MOSFET N LDO2 = 1.5V + Q4 MOSFET N LDO1 = 1.8V C12 330uF
+
C10 330uF +
C11 330uF
Revision: May 13, 2004
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SC1109
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VCC to GND STBY to GND BST to GND PHASE to GND LDOSx Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Seconds Thermal Resistance Junction to Ambient Thermal Impedance Junction to Case
Symbol
Maximum -0.3 to +7 -0.3 to +7 -0.3 to +20 -1 to +15 -0.3 to 5
Units V V V V V C C C C C/W C/W
TA TJ TSTG TL JA JC
0 to +70 0 to +125 -65 to +150 300 130 30
Electrical Characteristics
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70C
Parameter Supply (VCC) Supply Voltage Supply Quiescent Current Supply Operating Current Switching Section Output Voltage Line Regulation
(1) (1)
Symbol VCC ICCQ ICC VTT LOADREG LINEREG fOSC D VtripIlimit ItripIlimit
Conditions
MIN 4.4
T YP 5 8
MAX 5.25 12 20
UNIT S V mA mA V % %
VCC = 5V, SS/EN = 0V VCC = 5V, SS/EN > 1V IO = 2A IO = 0A to 6A Vin = 4.75V to 5.25V SC1109A 175 450 175 90 SC1109A SC1109B SC1109C VOSENSE to VO 3.9 180 180 112 SC1109B SC1109C 1.188
1.200 1 0.15 200 500 200 95 200 200 160 35 4.1 200
1.212
Load Regulation((1)
(1)
225 550 225 220 220 208
kHz kHz kHz % mV mV uA dB
Oscillator Frequency Oscillator Max Duty Cycle Current Limit trip (Vin-VPHASE) OscillatorGain (AOL) Threshold Hysteresis Power Good Power Good Threshold Voltage Soft Start / Enable SS/EN Source current SS/EN Sink current Shutdown Voltage
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(2) (2) (3)
GAINVTT VCCHIGH VCCHYST PGth IsourceSS/EN IsinkSS/EN VSS/EN
Under Voltage Lock Out 4.4 V mV 112 10 2 600
2
88 VSS/EN = 1.5V VSS/EN = 1.5V 5 1
% A A mV
12 3 650
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SC1109
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70C
Parameter Internal Drivers Peak DH Source Current Peak DH Sink Current Peak DL Source Current Peak DL Sink Current Dead time Linear Sections Standby Voltage Standby Quiescent current Tracking Difference(1)(4) Output Voltage LDO1 Output Voltage LDO2 Load Regulation Line Regulation LDOS(1,2) Input Impedance(3) Gain (AOL)(3)
Symbol
Conditions
MIN
TYP
MAX
UNITS
IsourceDH IsinkDH IsourceDL IsinkDL TDEAD
BST-DH = 4.5V DH-PHASE = 3.1V DH-PHASE = 1.5V VCC-DL = 4.5V DL-GND = 3.1V DL-GND = 1.5V
500 500 100 500 500 100 40 100
mA mA mA mA mA mA ns
VSTBY ISTDBYQ DeltaTRACK VLDO1 VLDO2 LOADREG LINEREG ZIN GAINLDO LDOS (1,2) to GATE (1,2) IO = 0 to 4A, Vin = 3.3V IO = 0 to 4A, Vin = 3.3V IO = 0 to 4A, Vin = 3.3V Io = 2A, Vin = 3.13V to 3.47V VSTBY = 5V, SS/EN = 0V
4.4
5
5.25 9
V mA mV
200 1.782 1.470 1.818 1.500 0.3 0.3 10 50 1.854 1.530
V V % % k dB
Notes: (1) All electrical characteristics are for the application circuit on page 16. (2) Soft start function is performed after Vcc is above the UVLO and SS/EN is above 600mV. The Soft start capacitor is then charged at a 10uA constant current until SS/EN is charged to above 1V. (3) Guaranteed by design (4) Tracking Difference is defined as the delta between 3.3V Vin and the LDO1, LDO2 output voltages during the linear ramp up until regulation is achieved. The tracking voltage difference might vary depending on MOSFETs RdSON, and load conditions. (5) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1109
POWER MANAGEMENT Pin Configuration
Top View
LDOS1 GATE1 STBY BCAP+ BCAPGND PHASE DL
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
Top View
LDOS2 GATE2 SS/EN VOSENSE PWRGD VCC BST DH LDOS1 GATE1 STBY BCAP+ BCAPGND PHASE DL
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
(SC1109A/B)
LDOS2 GATE2 SS/EN VOSENSE OCSET VCC BST DH
Ordering Information
Part Number (1) SC1109ACSTR SC1109BSTR SC1109CSTR SC1109EVB P ackag e SO-16 SO-16 SO-16 Linear Voltage 1.8V/1.5V 1.8V/1.5V 1.8V/1.5V PWM Frequency 200kHz 500kHz 200kHz Evaluation Board Over Current set Internal Internal External Temp Range (TJ) 0 to 125C 0 to 125C 0 to 125C
(SC1109C)
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name LDOS1 GATE1 STBY BC AP+ BC APGND PHASE DL DH BST VC C PWRGD OCSET 13 14 15 16 VOSENSE SS/EN GATE2 LDOS2 Pin Function Sense Input for LDO1. Gate Drive Output LDO1 (1.8V). 5V Standby Input, supplies power for Ref, Charge Pump, Oscillator and FET controllers. Should be present prior to other voltages and switched off last. Positive Connection to Boost Capacitor. Negative Connection to Boost Capacitor. Ground. Phase Node. Low Side Driver Output. High Side Driver Output. Boost Input. Power Supply Input. Open Colector Power Good Flag for 1.2V Outpu t(SC1109A, and SC1109B). Over current set pin for the PWM (SC1109C). A resistor to the Mosfe'ts supply will program the over current level. Output Sense Input for 1.2V Output. Soft Start/Enable. Gate Drive output LDO2 (1.5V). Sense Input for LDO2.
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SC1109
POWER MANAGEMENT Block Diagram
VCC
VBG
1.2V Bandgap UVLO 200mV OVER CURRENT
+ -
+ -
-10% +10% HIGH SIDE DRIVE
BST DH PHASE
SHOOT THRU CONTROL
-
PWRGD
+
OSCILLATOR
+
PWM
VCC R Q S
LOW SIDE DRIVE
VOSENSE
VCC VBG
+
ERROR AMP
+
SET DOMINATES
DL GND
SC1109A/B
SS/EN
S
10uA 0.8V
Q + R
HICCUP LATCH FAULT LOW SIDE OFF
SS/EN
+
0.6V
5VSTBY
2uA
5VSTBY
VBG
+ -
GATE2 LDOS2
5VSTBY
5VSTBY
CHARGE PUMP
STBY
OSCILLATOR
VBG
+ -
GATE1 LDOS1
BCAP+
BCAP-
VCC
VBG
1.2V Bandgap UVLO
160uA
+ -
OVER CURRENT
+ -
OCSET BST
HIGH SIDE DRIVE
DH PHASE
OSCILLATOR SHOOT THRU CONTROL
PWM
VCC R Q S
LOW SIDE DRIVE
VOSENSE
VCC VBG
+
ERROR AMP
+
SET DOMINATES
DL GND
SC1109C
SS/EN
S
10uA 0.8V
Q + R
HICCUP LATCH FAULT LOW SIDE OFF
SS/EN
+
0.6V
5VSTBY
2uA
5VSTBY
VBG
+ -
GATE2 LDOS2
5VSTBY
5VSTBY
CHARGE PUMP
STBY
OSCILLATOR
VBG
+ -
GATE1 LDOS1
BCAP+
BCAP-
Marking Information
SC1109ACS yyww xxxxx
SC1109A
SC1109BS yyww xxxxx
SC1109B
SC1109CS yyww xxxxx
SC1109C
yyww xxxxx
= Datecode (Example: 9912) = Semtech Lot # (Example: 90101)
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SC1109
POWER MANAGEMENT Application Information
THEORY OF OPERATION The SC1109 has integrated a synchronous buck controller and two Low drop out regulator controllers into a 16 Pin SOIC package. The switching regulator provides a 1.2V (VTT) bus termination voltage for use in AGTL (Assisted Gunning Transceiver Logic), while the dual LDO regulators provide 1.5V, and 1.8V to power up the Chip set and the Clock circuitry used in Pentium(R) III Motherboards. SUPPLIES Two supplies, VSTBY, and VCC are used to power the SC1109 . VSTBY supply provides the bias for the Internal Reference, Oscillator, and the LDO FET controllers. This supply should always be brought up first and turned off last in accordance with PC power configuration requirements. The VCC supply provides the bias for the Power Good circuitry, and the high side FET Rdson sensing/ over current circuitry, VCC also is used to drive the low side MOSFET gate. An external 12V supply or a classical boot strapping technique can provide the gate drive for the upper Mosfet. PWM CONTROLLER SC1109 is a voltage mode buck controller that utilizes an internally compensated high bandwidth error amplifier to sense the VTT output voltage. External compensation components are not needed and a stable closed loop response is insured due to the internal compensation. START UP SEQUENCE Initially during the power up, the SC1109 is in under voltage lockout condition. The latch (SET dominant) in the hiccup section is set , and the SS/EN pin is pulled low by the 2A soft start current source. Mean while, the high side and low side gate drivers DH, and DL are kept low. Once the VCC exceeds the UVLO threshold of 4.2V, the latch is reset and the external soft start capacitor starts to be charged by a 10A current source. The gate drives are still kept off until the soft start capacitors voltage rises above 600mV, when the low side gate is turned on, and the high side gate is kept off.
Soft start
The gate drive status stays the same until the capacitors voltage reaches 1V, when the error amplifier output starts to cross the oscillator triangular ramp of 1V to 2V. As the SS/EN pin continues to rise, the error amplifier output also rises at the same rate and the duty cycle increases. Once the VTT output has reached regulation and is within 1.2V 12% , an open collector power good flag is activated, and the error amplifier output will no longer be clamped to the SS/EN voltage and will stay between 1V to 2V and maintain regulation of 1%. The SS/EN voltage continues to rise up to 2.5V and will stay at that voltage level during normal operation.
Vcc
PowerGood
PhaseNode
If an over current condition occurs, the SS/EN pin will discharge by a 2A current source, from 2.5V to 800mV. During this time both DH, and DL will be turned off. Once the SS/EN reaches 800mV, the low side gate will be turned on, and the SS/EN pin will again start to be charged by the 10A current source, and the same soft start sequence mentioned above will be repeated. OVER CURRENT SC1109A/B monitor the Upper MOSFETs Rdson voltage drop due to an over current condition. This method of current sensing minimizes any unnecessary losses due to external sense resistance.
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SC1109
POWER MANAGEMENT Application Information (Cont.)
An internal comparator with a 200mV reference monitors the Drop across the upper FET, Once the Vdson of the MOSFET exceeds the 200mV limit, the low side gate is turned on and the upper FET is turned off. Also an internal latch is set and the soft start capacitor is discharged. Once the lower threshold of the soft start circuit is crossed, the same softstart sequence mentioned previously is repeated. This sequence is repeated until the over condition is removed. GATE DRIVERS The Low side gate driver is supplied from VCC and provide a peak source/sink current of and 500mA. The high side gate drive is also capable of sourcing and sinking peak currents of 500mA. The high side MOSFET gate drive can be provided by an external 12V supply that is connected from BST to GND. The actual gate to source voltage of the upper MOSFET will approximately equal 7V (12V-VCC). If the external 12V supply is not available, a classical boot strap technique can be implemented from the VCC supply. A boot strap capacitor is connected from BST to Phase while VCC is connected through a diode (Schottky or other fast low VF diode) to the BST. This will provide a gate to source voltage approximately to VCC-Vdiode drop.
Low er Gat e
Upper Gate
Lower Gate
PhaseNode
Low er Gat e
PhaseNode
Vtt Sho rted
Upper Gate Lo wer Gate
Shoot through control circuitry provides a 100ns dead time to ensure both upper and lower MOSFET will not turn on simultaneously and cause a shoot through condition. DUAL LDO CONTROLLERS SC1109 also provides two low drop out linear regulator controllers that can be used to generate a 1.8V and a 1.5V output. The LDO output voltage is achieved by controlling the voltage drop across an external MOSFET from a 3.3V supply voltage. The output voltage is sensed at the LDOS pin of the SC1109 and compared to an internal reference. The gate drive to the external MOSFET is then adjusted until regulation is achieved. In order to have sufficient voltage to the gate drives of the external MOSFET, an internal charge pump is utilized to boost the gate drive voltage to about two times the VSTBY.
The SC1109C utilizes an internal current source and an external resistor connected from the OCSET pin to the Mosfet's supply to program a current limit level. This limit is programmable by choosing the resistor according to the level required. To reduce any noise pick up a 1nF capacitor should be placed across the programing resistor. The device operation is similar to the SC1109A/B during the over current condition as mentioned above.
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SC1109
POWER MANAGEMENT Application Information (Cont.)
The internal charge pump charges an external Bucket capacitor to VSTBY and then connects it in series with VSTBY to the LDOs supply at a frequency of about 200kHz. This ensures sufficient gate drive voltage for the LDOs independent of the VCC or the 12V external supply being available due to start up timing sequence from the silver box. LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1109 PWM controller. High currents switching are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short, top FET gate charge currents flow in this trace.
3.3V Vin
1.8V Vout 1.5V Vout
The LDO1, and LDO2 output voltages are forced to track the 3.3V input supply. This feature ensures that during the start up application of the 3.3V, the LDO1, and LDO2 outputs track the 3.3V within 200mV typical until regulation is achieved. However, the VSTBY should be established at least 500us, to allow the charge pump to reach its maximum voltage, before the linear section will track within 200mV. This tracking will sequence the correct start up timing for the external Chipset and Clock circuitry.
12V IN 5V STBY 5V IN
U4 VCC BCAP+
SC1109A STBY BST DH +
BCAPSS/EN PWRGD VOSENSE GATE2 LDOS2
PHASE
VTT
DL GND GATE1 LDOS1
+
3.3V IN
Heavy Lines indicate high current paths.
1.5V + C10 330uF + + 1.8V
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SC1109
POWER MANAGEMENT Application Information (Cont.)
4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents sre supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1109 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. 6) BST for the SC1109 should be supplied from the 12V supply, the BST pin should be decoupled directly to GND by a 0.1mF ceramic capacitor, trace lengths should be as short as possible. If a 12V supply is not available, a classical boot strap method could be implemented to achieve the upper MOSFETs gate drive. 7) The Phase connection should be short . 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s).
5V
+
Vout +
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SC1109
POWER MANAGEMENT Application Information (Cont.)
COMPONENT SELECTION SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from: The maximum inductor value may be calculated from:
L R ESR C (VIN - V O ) It
RESR
Vt It
Where Vt = Maximum transient voltage excursion It = Transient current step
For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies.
Each Capacitor C (uF) 330 330 1500 ESR (m) 60 25 44 Total Qty Rqd. C (uF) 2000 990 7500 ESR (m) 10 8.3 8.8
The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
I L RIPPLE = V IN 4 L f OSC
Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as:
Technology
Low ESR Tantalum OS-CON Low ESR Aluminum
6 3 5
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above.
P COND where
2 = IO R
DS ( on )
= duty
cycle
VO V IN
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
P SW = I O V IN 10
-3
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SC1109
POWER MANAGEMENT Application Information (Cont.)
or more generally,
IO VIN ( t r + t f ) fOSC 4 c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: PSW =
P RR =Q
RR
FET Type IRL3402S IRL2203 Si4410
RDS(on) (m) 15 10.5 20
PD(W) 1.33 0.93 1.77
Package D2PAK D2PAK SO-8
V
IN
f OSC
To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET Type IRL3402S IRL2203 Si4410 RDS(on) (m) 15 10.5 20 PD(W) 1.69 1.19 2.26 Package D2PAK D2PAK SO-8
Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below:
Temperature rise ( 0C) FET Type IRL3402S IRL2203 Si4410 Top FET 67.6 47.6 180.8 Bottom FET 53.2 37.2 141.6
BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by:
P COND
2 = IO R DS ( on )
It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.
(1 - )
For the example above:
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SC1109
POWER MANAGEMENT SC1109 Gain & Phase Margin
SC1109A Gain & Phase Margin
50 200
180 40 160 30
Gain
Phase Margin (Deg.)
140
Gain (dB)
20
120
10
Phase Margin
100
80 0 60 -10 40
-20 10 100 1,000 frequency(Hz) 10,000
20 100,000
Typical VTT Gain/Phase plot at Vin = 5V, Iout = 3A
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SC1109
POWER MANAGEMENT Typical Characteristics
SC1109 Quiescent Current vs Ta
SC1109 Quiescent Current (Linear) vs Ta
4.45 4.40 4.35 4.30
7.90 7.85 7.80 7.75
Icc (mA)
Vcc = 5.25 Vcc = 4.75
7.70 7.65 7.60 7.55 7.50 7.45 7.40 0 10 20 30
Ta (C.)
ISTBYQ (mA)
4.25 4.20 4.15 4.10 4.05 4.00 3.95
Vcc = 5.25 Vcc = 4.75
0 10 20 30 40 50 60 70
40
50
60
70
Ta (C.)
Typical Icc (Switching section)
SC1109 Soft start Source Current vs Ta
9.32
Typical ISTBYQ (Linear section)
SC1109 Soft start Source Current vs Ta
8.10
Vcc = 5.25V , Vss = 0V
9.30 9.28 9.26
Vcc = 4.75V , Vss = 1.5V
8.08
Vcc = 4.75V , Vss = 0V
Vcc = 5.25V , Vss = 1.5V
8.06 8.04
Iss (uA)
Iss (uA)
0 10 20 30 40 50 60 70
9.24 9.22 9.20 9.18 9.16 9.14
8.02 8.00 7.98 7.96 7.94 0 10 20 30 40 50 60 70
Ta (C.)
Ta (C)
Typical Soft start source Current Vss = 0V
SC1109 Soft start Sink Current vs Ta
9.30 9.28 9.26 9.24 9.22
Typical Soft start source Current Vss = 1.5V
SC1109 Soft start Sink Current vs Ta
1.80
Vcc = 5.25V , Vss = 0V Vcc = 4.75V , Vss = 0V
1.79
Vcc = 4.75V , Vss = 1.5V Vcc = 5.25V , Vss = 1.5V
1.79
Iss (uA)
9.20 9.18 9.16 9.14 9.12 9.10 9.08 0 10 20 30 40 50 60 70
Iss (uA)
1.78
1.78
1.77
1.77 0 10 20 30 40 50 60 70
Ta (C.)
Ta (C.)
Typical Soft start sink Current Vss = 0V
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Typical Soft start sink Current Vss = 1.5V
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SC1109
POWER MANAGEMENT Typical Characteristics
SC1109 Tracking Difference (Io LDO1,2 = 2A) vs Ta
280.0
260.0
240.0
Delta (mV)
220.0
200.0
LDO2 LDO2
Vcc = 4.75 Vcc = 5.25 Vcc = 4.75 Vcc = 5.25
20 30 40 50 60 70
180.0
LDO1 LDO1
160.0 0 10
Ta (C.)
Typical Tracking difference (BetweenVin3.3 & LDO)
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SC1109
POWER MANAGEMENT Typical Characteristics
SC1109 (VTT) Eff. vs Iout (Vin = 5.0V) 90.0% 80.0% 70.0% Efficiency(%) 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0.00 2.00 4.00 Iout_Vtt (Amps) 6.00 8.00
IRL3103R(V1.8,V2.5 No load)
SC1109 (VTT) Line Reg. vs Vin (Iout = 6.0A) 0.350% 0.300% Line Reg.(%) 0.250% 0.200% 0.150% 0.100% 0.050%
IRL3103R(V1.8,V2.5 No load)
0.000% 4.000 4.500 5.000 5.500 Vin (V)
6.000 6.500 7.000
Typical VTT Efficiency at Vin=5V
Typical VTT Line Regulation at Iout = 6 Amps
SC1109 (VTT) Load Reg. vs Iout (Vin = 5.0V) 0.000% -0.100% Load Reg.(%) -0.200% -0.300% -0.400% -0.500% -0.600% 0.00
IRL3103R(V1.8,V2.5 No load)
SC1109 (VTT) Line Reg. vs Vin (Iout = 3.0A) 0.120% 0.100% Line Reg.(%) 0.080% 0.060% 0.040% 0.020% 0.000% 4.700 4.800
IRL3103R(V1.8,V2.5 No load)
2.00
4.00 Iout_Vtt (Amps)
6.00
8.00
4.900 5.000 5.100 Vin (V)
5.200 5.300
Typical VTT Load Regulation at Vin=5V
Typical VTT Line Regulation at Iout = 3 Amps
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SC1109
POWER MANAGEMENT Evaluation Board Schematic
12V IN GND 5V STBY GND 5V IN
J1 J2 J3 J4 J5 C2 + R1 10k 1500uF C5 + 1500uF C3 0.1uF R5 0 11 C6 0.1uF 4 C7 0.1uF 5 14 12 C16 0.1uF C12 0.1uF 13 15 16 C4 0.1uF C1 0.1uF
5V IN J6
U1 VCC BCAP+
SC1109A/B STBY BST DH
3 10 9 7
R2 0 R4 2.2 D1 R3 0 D1N4148
Q1 IRLR3103 L1 4uH
1.2V 6A
VTT J7 J9 C11 0.1uF VTT
GND
J8
GND J10 POWER GOOD J11
BCAPSS/EN PWRGD VOSENSE GATE2 LDOS2
PHASE
DL GND GATE1 LDOS1
8 6 2 1
Q2 C8 IRLR3103
+
C9
+
C10 +
1500uF 1500uF 1500uF GND J12 J13 GND
3.3V IN J14 Q3 IRLR3103 Q4 IRLR3103 1.8V J15 GND J17 + C14 330uF GND J18 + C15 330uF GND J19 J16
+
C13 330uF
1.5V
12V IN GND 5V STBY GND 5V IN
J1 J2 J3 J4 J5 C2 + R1 TBD 1500uF C5 + 1500uF C3 0.1uF R5 0 11 C6 0.1uF 4 C7 0.1uF 5 14 12 C12 0.1uF 13 15 16 C4 0.1uF C1 0.1uF
5V IN J6 C16 1nF
U1 VCC BCAP+
SC1109C STBY BST DH
3 10 9 7 D1
R2 0 R4 2.2
Q1 IRLR3103 L1 4uH
1.2V 6A
VTT J7 J9 C11 0.1uF VTT
GND
J8
GND J10 OCSET J11
BCAPSS/EN OCSET VOSENSE GATE2 LDOS2
PHASE
DL GND GATE1 LDOS1
8 6 2 1
R3 0 D1N4148
Q2 C8 IRLR3103
+
C9
+
C10 +
1500uF 1500uF 1500uF GND J12 J13 GND
3.3V IN J14 Q3 IRLR3103 Q4 IRLR3103 1.8V J15 GND J17 + C14 330uF GND J18 + C15 330uF GND J19 J16
+
C13 330uF
1.5V
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SC1109
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Qty. 8 5 3 1 1 1 9 1 2 2 1 1 1 1 1 4 1 3 1 1 Reference C1,C3,C4,C6,C7,C11,C12,C13 C2,C5,C8,C9,C10 C13,C14,C15 C 16 D1 J1 J2,J4,J8,J10,J12,J13,J17,J18,J19 J3 J5,J6 J7,J9 J11 J1 4 J1 5 J1 6 L1 Q1,Q2,Q3,Q4 R1 R2,R3,R5 R4 U1 0.1F 1500F 330F 0.1uF(SC1109A/B), 1nF(SC1109C) D1N4148 12V IN GND 5V STBY 5V IN VTT POWER GOOD / OCSET 3.3V IN 2.5V 1.8V 4H IRLR3103 10k (SC1109A/B), TBD(SC1109C) 0 2.2 SC1109A/B/C Part
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SC1109
POWER MANAGEMENT Evaluation Board Gerber Plots
Board Layout Assembly Top
Board Layout Bottom
Board Layout Top
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SC1109
POWER MANAGEMENT Outline Drawing - SO-16
Land Pattern - SO-16
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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